This invention relates to testing asynchronous logic circuitry, and more particularly to methods and apparatus for facilitating the testing of such circuitry.
Scan testing is a well-known technique for testing synchronous logic circuitry to determine whether or not the circuitry has the design required to enable it to function properly under all circumstances and/or whether the circuitry has been fabricated properly and without defects. However, scan testing assumes that signals such as the clock, preset, and clear of each storage register ("flip-flop") in the logic circuitry come directly from an input terminal (pin) of the circuitry. This is generally not true for asynchronous logic circuitry where one or more of such signals may be generated by logic included in the circuitry to be tested. This makes it impossible to test asynchronous logic either at all or as completely as would be desired using scan testing.
It is therefore an object of this invention to provide methods and apparatus for facilitating the scan testing of asynchronous logic.
It is another object of this invention to provide methods and apparatus for allowing more complete scan testing of asynchronous logic.